Basically, been ... uh... copy-pasting the TNG one, then going, "Well, I'll say that whilst some things like the warp core were developed for the galaxy only in the very last years of the program before the galaxy and enterprise were commissioned, others like the computers were already developed by the mid-50s, simply made bigger as the ship design neared completion.4.1 Computer System
The main computer system of the USS Voyager is probably the most important single operational element of the starship next to the crew. The computer is directly analogous to the autonomic nervous system of a living being, and is responsible in some way for the operation of virtually every other system of the vehicle.
Crew interface for the main computer is provided by the Library Computer Access and Retrieval System software, usually abbreviated as LCARS. LCARS provides both keyboard and verbal interface ability, incorporating highly sophisticated artificial intelligence routines and graphic display organization for maximum crew ease-of-use.
Computer Cores
The heart of the main computer system is a set of four redundant main processing cores. Any of these four cores is able to handle the primary operational computing load of the entire vessel. The Two Primary Computer Cores are located just aft of the spare warp core compartment across decks 10, 11 and 12, while the Secondary Computer Cores are located amidships across decks 7 and 8. Each computer core incorporates a series of miniature subspace field generators, which creates a symmetrical (nonpropulsive) field distortion of 5830 millicochranes within the faster-thanlight (FTL) core elements. This permits the transmission and processing of optical data within the core at rates significantly exceeding lightspeed.
The two main cores in the Secondary Hull run in parallel clock-sync with each other, providing 100% redundancy. In the event of any failure in either core, the other core is able to instantly assume the total primary computing load for the ship with no interruption, although some secondary and recreational functions (such as holodeck simulations) may be momentarily suspended. The third and fourth cores, located in the Primary Hull, serves as a backup to the first two.
Core elements are based on FTL nanoprocessor units arranged into optical transtator clusters of 1,024 segments. In turn, clusters are grouped into processing modules composed of 256 clusters controlled by a bank of sixteen isolinear chips. Each Primary core comprises three levels, each level containing four modules. Both Secondary Cores comprise of two levels, each level containing only three modules.
In Total, the USS Voyager has 36 Processing Modules, containing 9,216 optical transtator clusters, made up of 9,437,184 FTL Nanoprocessor unit segments. In total, these FTL Nanoprocessor units/optical transtator clusters are controlled by 576 isolinear chips. For Comparison, the Galaxy class USS Enterprise has three identical computer cores of seven levels each, each level containing four modules of the same capacities, reaching totals of 84 processor modules, 21,504 optical transtator clusters of 22,020,096 FTL nanoprocessor Units. While the Intrepid class design has less than half the FTL nanoprocessors, due the advances that allow them to operate at faster FTL frequencies, the USS Voyager’s computer cores are only 20% less powerful. In Single-threaded operation, the USS Voyager’s computers are 75% faster than the USS Enterprise’s.
Core Memory
The physical memory storage in the computer cores are evenly distributed to each of the Processor Modules, with all 36 individually containing 1024 storage modules of 144 isolinear optical storage chips. Under LCARS software control, these modules provide average dynamic access to memory at 3,276,800 kiloquads/sec, or 400 megaquads/sec.
Each isolinear optical storage chip used by the USS Voyager is an improved design based from those used by the Galaxy class and has a storage capacity of 67,108,864 quads, or 8,192 kiloquads, or 1 megaquad, compared to the 2 kiloquads of those of the USS Enterprise. All 10,616,832 chips give a theoretical storage capacity of 356.2 trillion quads/43.5 billion kiloquads/5.3 million megaquads or 647 gigaquads of information (compare the USS Enterprise, with just 6,048 megaquads). However, as the storage chips are able to be used not just as long-term storage but as short-term random-access memory, the actual storage capacity is only counted by data stored. Typically, only a quarter of a core’s chips are actually used as long-term storage, the rest used for random-access memory for the many memory-intensive operations (including the very-high-memory-density holographic systems)
The main cores are tied into the ship's optical data network by means of a series of MJL junction links which bridge the subspace boundary layer. There is a 12% Doppler loss in transmission rate across the boundary, but the resulting increase in processing speed from the FTL core elements more than compensates.
Subprocessors
A network of 38 quadritronic optical subprocessors is distributed throughout the ship, augmenting the main cores. Within the habitable volume of the ship, most of these subprocessors are located near main corridor junctions for easy access. While these subprocessors do not employ FTL elements, the distributed processing network improves overall system response and provides redundancy in emergency situations. Each subprocessor is linked into the optical data network, and most also have a dedicated optical link to one or more of the main cores.
The Bridge and Main Engineering each has seven dedicated and ten shared subprocessors which permit operations even in the event of main core failure. These bridge and engineering subprocessors are linked to the main cores by means of protected optical conduits, which provide alternate control linkages in the event of a primary optical data network failure. Further redundancy is provided by dedicated short-range radio frequency (RF) links, providing emergency data communications with the bridge. Additional dedicated subprocessors can be installed as needed to support mission-specific operations.
Virtually every control panel and terminal within the ship is linked to a subprocessor or directly into the optical data network. Each active panel is continually polled by LCARS at 20 millisecond intervals so that the local subprocessor and/or the main core is informed of all keyboard or verbal inputs. Each polling inquiry is followed by a 38 nanosecond compressed data stream, which provides panel update information. This data stream includes any requested visual or audio information for panel output.
Short-range RF data links are available throughout the ship to provide information transmission to portable and handheld devices such as tricorders and personal access display devices.
This integrated network of computers, subprocessors and panels forms the “nervous” system of the ship and permits continuous real-time analysis of the ship’s operating status. The network is specifically designed to permit independent operation of remaining system elements in the event of a wide variety of partial system failures.
4.2 Isolinear Optical Chips
Isolinear optical chips are the primary software and data storage medium employed throughout the USS Voyager’s computer systems. These nanotech devices represent a number of significant advances over the crystal memory cards used in earlier systems.
These chips make use of single-axis optical crystal layering to achieve subwavelength switching distances. Nanopulse matrix techniques yield a total memory capacity of 8 kiloquads per chip in standard holographic format – an improvement made in the decade since the commissioning of the first Galaxy class starship, whose Isolinear chips only had a capacity of 2.15 kiloquads.
Like earlier crystal memory devices, isolinear chips optimize memory access by employing onboard nanoprocessors. In these new devices, however, higher processing speeds permit individual chips to manage data configuration independent of LCARS control, thus reducing system access time by up to 12%. Additionally, the chip substrate is infused with trace quantities of superconductive platinum/iridium, which permits FTL optical data transmission when energized by a Computer Core’s subspace flux. This results in a dramatic increase in processing speed when used in one of ship’s Computer Cores.
Isolinear chips can be ruggedized with the application of a protective tripolymer sealant over the refractive interface surface. This allows the chip to be handled without protective gloves. When so treated, isolinear chips are used as a convenient form of information transport. Many portable data-handling devices such as tricorders, PADDs and optical chip readers are able to read and write to standard format isolinear chips.
To Note:
What I'm saying for the Galaxy is that for the Isolinear chips - it's got almost 24.8 million chips in its computers, because each "Processor Module" (of which each of the three cores has four per each of their 7 levels for 84 total Processor Modules) has 2048 Storage Modules each of which is 144 isolinear storage chips. because otherwise the Ent just has 589,824 kiloquads of information storage...
and I'm using x8192 for each stepping from quad<kilo<mega<giga.
Now.. this "Galaxy's chips were developed by the 2350s" and "Intrepids in the late-2360s... say, about fifteen-twenty years of advances to put into place (Includes the bioneural gelpacks for "smarter" processing, not necessarily faster through brute force)
1983: Rodime released the first 3.5-inch format hard drive which stored 10 MB.
2003: Western Digital introduces the 10,000 RPM SATA hard drive with 37 GB of storage.
10 MB: 10,000,000 bytes... or is that 10,485,760 (depends!)
37 GB: Either 37,000,000,000 bytes, or 39,728,447,488. ... so about a 3,800-ish percent increase.
apply that to the '2.15 kiloquad' isolinear chip of the galaxy. ~ 8,170 kiloquads. OR... as I'm going for "8192 quads = 1 kiloquad and 8192 kiloquads =1 megaquad", it's a 1 Megaquad chip now... and the ones used on DS9 (say, when bashir recieved new holosuite programs) still needed a couple of them. Worf's less-sophisticated *cough* sorry, Worf's Klingon Operas were not quite so memory-intensive, so his fit one or more program per chip... say a single holosuite program could be anywhere between
To note, for the Prometheus episode (Ship in a Bottle) in season 4, the EMH had to 'leave behind' 12 megaquads. 12 megaquads in a program that was probably NOT a fraction of that, but that is still a 'big enough chunk' (I'll say his program is more than 12 megaquads as of his first activation, and those 12 he left behind were NOT all the 'data weight' he'd gained since then...
)but say 24 megaquads is his program size by endgame... if the Enterprise has a capacity of 6,048 megaquads... thats.... 0.5% for the EMH. 1% on a ship that probably has holodeck programs more sophisticated, many of, thereby those being more than 24 megaquads each (1% is 60 megaquads).
of course, this is not including the fact that the chips are both storage and RAM for the ship.
I'll say at "up to 25% storage, 75 and up as RAM", with "Librarys" specifically built to instead act as more pure data storage where those percents are flipped.
Now, Galaxy is 24.7 million of these chips.
if voyager was just 10.6 million of those 2 kiloquad chips...Voyager would only have 2,592 megaquad of storage. not *5.3 million*.
a quarter of that 2,592 as storage, then the EMH would take up about 5% of that storage. FIVE.
So... yeah.
that storage density increase percentage fits real-world increases kind of, if you take isolinear chips as developed to the Ent's level in the 40s to 50s, with Voyagers' level being the Latest and Greatest.
To note:
in gigaquad: Enterprise? 0.74. Voyager? 648!
